1. Field of the Invention
The present invention relates to a bundled memory and a manufacture method for a bundled memory with an external input/output bus, and particularly to a bundled memory and a manufacture method for a bundled memory with an external input/output bus that can utilize at least one mask layer formed over a plurality of scribe lines to form electrical connection coupled between input/output buses of any two memory dies.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram illustrating a wafer 11 with a plurality of memory dies and a magnified structure of a memory die 12 according to the prior art, where the wafer 11 includes a plurality of repeating units, and each repeating unit is called a memory die (e.g. the memory die 12). As shown in FIG. 1, in the wafer 11, the memory die 12 is isolated from other dies and separated from an adjacent memory die 14 through a scribe line 13. In addition, no signal is connected over die boundaries between the memory die 12 and the memory die 14. After fabrication of the wafer 11 is completed, the wafer 11 is scribed to the plurality of memory dies (e.g. the memory die 12 and the memory die 14) into individual memory devices. As shown in FIG. 1, after the memory die 12 is cut from the wafer 11, the memory die 12 has an input/output circuit 16 and a complete set of bounding pads 17 to communicate with external circuits.
However, after fabrication of the wafer 11 is completed, memory depth and bus width of the memory die 12 and the memory die 14 are fixed. For example, the memory depth and the bus width of the memory die 12 and the memory die 14 are 2M and 32, bits, respectively. Therefore, a memory die provided by the prior art is less flexible for a user.